Deep Learning: Hardware Design

Deep Learning: Hardware Design
Author :
Publisher :
Total Pages : 251
Release :
ISBN-10 : 9798668283231
ISBN-13 :
Rating : 4/5 ( Downloads)

Book Synopsis Deep Learning: Hardware Design by : Albert Liu Oscar Law

Download or read book Deep Learning: Hardware Design written by Albert Liu Oscar Law and published by . This book was released on 2020-07-21 with total page 251 pages. Available in PDF, EPUB and Kindle. Book excerpt: 2nd edition. With the Convolutional Neural Network (CNN) breakthrough in 2012, the deep learning is widely appliedto our daily life, automotive, retail, healthcare and finance. In 2016, Alpha Go with ReinforcementLearning (RL) further proves new Artificial Intelligent (AI) revolution gradually changes our society, likepersonal computer (1977), internet (1994) and smartphone (2007) before. However, most of effortfocuses on software development and seldom addresses the hardware challenges:* Big input data* Deep neural network* Massive parallel processing* Reconfigurable network* Memory bottleneck* Intensive computation* Network pruning* Data sparsityThis book reviews various hardware designs range from CPU, GPU to NPU and list out special features toresolve above problems. New hardware can be evolved from those designs for performance and powerimprovement* Parallel architecture* Convolution optimization* In-memory computation* Near-memory architecture* Network optimizationOrganization of the Book1. Chapter 1 introduces neural network and discuss neural network development history2. Chapter 2 reviews Convolutional Neural Network model and describes each layer function and itsexample3. Chapter 3 list out several parallel architectures, Intel CPU, Nvidia GPU, Google TPU and MicrosoftNPU4. Chapter 4 highlights how to optimize convolution with UCLA DCNN accelerator and MIT EyerissDNN accelerator as example5. Chapter 5 illustrates GT Neurocube architecture and Stanford Tetris DNN process with in-memorycomputation using Hybrid Memory Cube (HMC)6. Chapter 6 proposes near-memory architecture with ICT DaDianNao supercomputer and UofTCnvlutin DNN accelerator7. Chapter 7 chooses energy efficient inference engine for network pruning3We continue to study new approaches to enhance deep learning hardware designs and several topics willbe incorporated into future revision* Distributive graph theory* High speed arithmetic* 3D neural processing


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