Logic Synthesis Using Synopsys®

Logic Synthesis Using Synopsys®
Author :
Publisher : Springer Science & Business Media
Total Pages : 317
Release :
ISBN-10 : 9781475723700
ISBN-13 : 1475723709
Rating : 4/5 (709 Downloads)

Book Synopsis Logic Synthesis Using Synopsys® by : Pran Kurup

Download or read book Logic Synthesis Using Synopsys® written by Pran Kurup and published by Springer Science & Business Media. This book was released on 2013-06-29 with total page 317 pages. Available in PDF, EPUB and Kindle. Book excerpt: Logic synthesis has become a fundamental component of the ASIC design flow, and Logic Synthesis Using Synopsys® has been written for all those who dislike reading manuals but who still like to learn logic synthesis as practised in the real world. The primary focus of the book is Synopsys Design Compiler®: the leading synthesis tool in the EDA marketplace. The book is specially organized to assist designers accustomed to schematic capture based design to develop the required expertise to effectively use the Compiler. Over 100 `classic scenarios' faced by designers using the Design Compiler have been captured and discussed, and solutions provided. The scenarios are based both on personal experiences and actual user queries. A general understanding of the problem-solving techniques provided will help the reader debug similar and more complicated problems. Furthermore, several examples and dc-shell scripts are provided. Specifically, Logic Synthesis Using Synopsys® will help the reader develop a better understanding of the synthesis design flow, optimization strategies using the Design Compiler, test insertion using the Test Compiler®, commonly used interface formats such as EDIF and SDF, and design re-use in a synthesis-based design methodology. Examples have been provided in both VHDL and Verilog. Audience: Written with CAD engineers in mind to enable them to formulate an effective synthesis-based ASIC design methodology. Will also assist design teams to better incorporate and effectively integrate synthesis with their existing in-house design methodology and CAD tools.


Logic Synthesis Using Synopsys® Related Books

Logic Synthesis Using Synopsys®
Language: en
Pages: 317
Authors: Pran Kurup
Categories: Technology & Engineering
Type: BOOK - Published: 2013-06-29 - Publisher: Springer Science & Business Media

DOWNLOAD EBOOK

Logic synthesis has become a fundamental component of the ASIC design flow, and Logic Synthesis Using Synopsys® has been written for all those who dislike read
VHDL Coding and Logic Synthesis with Synopsys
Language: en
Pages: 417
Authors: Weng Fook Lee
Categories: Technology & Engineering
Type: BOOK - Published: 2000-08-22 - Publisher: Elsevier

DOWNLOAD EBOOK

This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of "synthesis tools" is the m
Logic Synthesis and Verification
Language: en
Pages: 474
Authors: Soha Hassoun
Categories: Computers
Type: BOOK - Published: 2001-11-30 - Publisher: Springer Science & Business Media

DOWNLOAD EBOOK

Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and th
Logic Synthesis and SOC Prototyping
Language: en
Pages: 260
Authors: Vaibbhav Taraate
Categories: Technology & Engineering
Type: BOOK - Published: 2020-01-03 - Publisher: Springer Nature

DOWNLOAD EBOOK

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design
Advanced ASIC Chip Synthesis
Language: en
Pages: 341
Authors: Himanshu Bhatnagar
Categories: Computers
Type: BOOK - Published: 2002 - Publisher: Springer Science & Business Media

DOWNLOAD EBOOK

This book describes advanced concepts and techniques for ASIC chip synthesis, physical synthesis, formal verification, and static timing analysis using the Syno