Download or read book Analysis & Optimization of Floor Planning Algorithms for VLSI Physical Design written by Dr. Ashad Ullah Qureshi and published by Concepts Books Publication. This book was released on 2022-07-01 with total page 33 pages. Available in PDF, EPUB and Kindle. Book excerpt: As prevailing copper interconnect technology advances to its fundamental physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization. Carbon nanotube (CNT) interconnects have emerged as promising replacement materials for copper interconnects due to their superior conductivity. Buffer insertion for CNT interconnects is capable of improving circuit timing of signal nets with limited buffer deployment. However, due to the imperfection of fabricating long straight CNT, there exist significant unidimensional-spatially correlated variations on the critical CNT geometric parameters such as the diameter and density, which will act the circuit performance. This dissertation develops a novel timing driven buffer insertion technique considering unidimensional correlations of variations of CNT. Although the fabrication variations of CNTs are not desired for the circuit designs targeting performance optimization and reliability, these inherent imperfections make them natural candidates for building highly secure physical unclonable function (PUF), which is an advanced hardware security technology. A novel CNT PUF design through leveraging Lorenz chaotic system is developed and we show that it is resistant to many machine learning modeling attacks. In summary, the studies in this dissertation demonstrate that CNT technology is highly promising for performance and security optimizations in advanced VLSI circuit design.