A Minimum Area VLSI (Very Large Scale Integrated Architecture for O(LOGN) Time Sorting

A Minimum Area VLSI (Very Large Scale Integrated Architecture for O(LOGN) Time Sorting
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Total Pages : 28
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ISBN-10 : OCLC:227616992
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Book Synopsis A Minimum Area VLSI (Very Large Scale Integrated Architecture for O(LOGN) Time Sorting by : G. Bilardi

Download or read book A Minimum Area VLSI (Very Large Scale Integrated Architecture for O(LOGN) Time Sorting written by G. Bilardi and published by . This book was released on 1983 with total page 28 pages. Available in PDF, EPUB and Kindle. Book excerpt: A generalization of a known class of parallel sorting algorithms is presented, together with a new architecture to execute them. A VLSI implementation is also proposed, and its area-time performance is discussed. It is shown that an algorithm in the class is executable in 0(logn) time by a chip occupying O(n2) area. The design is a typical instance of a 'hybrid architecture', resulting from the combination of well-known VLSI arrays as the orthogonal-trees and the cube-connected-cycles; it is also the first known to meet the AT21 = omega(n2log2n) lower bound for sorters of n words of length (1 + epsilon) and working in minimum 0(logn) time. (Author).


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